MU · USPTO Filings
Micron Technology, Inc. — Patent Applications
Recent USPTO patent applications filed under applicant “Micron Technology, Inc. / MICRON TECHNOLOGY, INC.” — pending requests, not granted patents. Where a filing continues an already-granted parent, the parent’s number is shown.
50
Tracked Applications
50
Continuations of Granted Parents
Recent Applications
Every row is a patent application — a pending request, not a granted patent. “Granted Parent” shows the parent patent number when a filing continues an already-granted family. Newest filings first. Source: USPTO Open Data Portal (public).
| Title | Filed | Application # | Status | Granted Parent |
|---|---|---|---|---|
| THREE-STATE PROGRAMMING OF MEMORY CELLS | 2026-02-12 | 19537939 | Docketed New Case - Ready for Examination | parent 12567463 |
| ADAPTIVE TIME SENSE PARAMETERS AND OVERDRIVE VOLTAGE PARAMETERS FOR WORDLINES AT CORNER TEMPERATURES IN A MEMORY SUB-SYSTEM | 2026-01-28 | 19462118 | Docketed New Case - Ready for Examination | parent 12554435 |
| APPARATUSES AND METHODS FOR DISTRIBUTING AND PROVIDING DATA PROTECTION FOR AUXILIARY DATA | 2026-01-27 | 19460901 | Docketed New Case - Ready for Examination | parent 12541428 |
| SAFE AREA FOR CRITICAL CONTROL DATA | 2026-01-27 | 19460956 | Docketed New Case - Ready for Examination | parent 12561069 |
| SYSTEM-DRIVEN HEALTH MONITORING OF A MEMORY DEVICE | 2026-01-27 | 19461072 | Docketed New Case - Ready for Examination | parent 12572418 |
| VOLTAGE WINDOW ADJUSTMENT | 2026-01-27 | 19460407 | Docketed New Case - Ready for Examination | parent 12547318 |
| CORRECTIVE READ WITH PARALLEL AUTO-READ CALIBRATION IN A MEMORY SUB-SYSTEM | 2026-01-26 | 19460227 | Docketed New Case - Ready for Examination | parent 12561072 |
| THREE-DIMENSIONAL STACKING SEMICONDUCTOR ASSEMBLIES WITH NEAR ZERO BOND LINE THICKNESS | 2026-01-26 | 19459803 | Docketed New Case - Ready for Examination | parent 12027498 |
| Memory Arrays Comprising Strings Of Memory Cells And Methods Used In Forming A Memory Array Comprising Strings Of Memory Cells | 2026-01-26 | 19459573 | Docketed New Case - Ready for Examination | parent 12557274 |
| ERASE PULSE LOOP DEPENDENT ADJUSTMENT OF SELECT GATE ERASE BIAS VOLTAGE | 2026-01-26 | 19459378 | Docketed New Case - Ready for Examination | parent 12555638 |
| SIGNAL ROUTING STRUCTURES INCLUDING A PLURALITY OF PARALLEL CONDUCTIVE LINES AND SEMICONDUCTOR DEVICE ASSEMBLIES INCLUDING THE SAME | 2026-01-26 | 19459520 | Docketed New Case - Ready for Examination | parent 12538821 |
| IDENTIFY THE PROGRAMMING MODE OF MEMORY CELLS BASED ON CELL STATISTICS OBTAINED DURING READING OF THE MEMORY CELLS | 2026-01-23 | 19458199 | Docketed New Case - Ready for Examination | parent 12537054 |
| MULTILEVEL PLATE LINE DECODING | 2026-01-23 | 19458341 | Docketed New Case - Ready for Examination | parent 12555634 |
| PLANE BALANCING IN A MEMORY SYSTEM | 2026-01-23 | 19458566 | Docketed New Case - Ready for Examination | parent 12541320 |
| SEMICONDUCTOR DEVICE HAVING MEMORY CELL ARRAY DIVIDED INTO PLURAL MEMORY MATS | 2026-01-23 | 19458344 | Docketed New Case - Ready for Examination | parent 12537048 |
| SOCKET DESIGN FOR A MEMORY DEVICE | 2026-01-23 | 19458532 | Docketed New Case - Ready for Examination | parent 12548621 |
| READ SOFT BITS THROUGH BOOSTED MODULATION FOLLOWING READING HARD BITS | 2026-01-23 | 19458530 | Docketed New Case - Ready for Examination | parent 12537064 |
| VERIFYING IDENTITY OF AN EMERGENCY VEHICLE DURING OPERATION | 2026-01-22 | 19456959 | Docketed New Case - Ready for Examination | parent 12536905 |
| Image Sensor with Analog Inference Capability | 2026-01-22 | 19456913 | Docketed New Case - Ready for Examination | parent 12538048 |
| COMPILER CONFIGURABLE TO GENERATE INSTRUCTIONS EXECUTABLE BY DIFFERENT DEEP LEARNING ACCELERATORS FROM A DESCRIPTION OF AN ARTIFICIAL NEURAL NETWORK | 2026-01-22 | 19457028 | Docketed New Case - Ready for Examination | parent 12536427 |
| Integrated Assemblies and Methods of Forming Integrated Assemblies | 2026-01-21 | 19454919 | Docketed New Case - Ready for Examination | parent 12557275 |
| WAFER ALIGNMENT FOR STACKED WAFERS AND SEMICONDUCTOR DEVICE ASSEMBLIES | 2026-01-21 | 19455451 | Docketed New Case - Ready for Examination | parent 12564067 |
| Integrated Circuitry, Memory Circuitry Comprising Strings of Memory Cells, and Method of Forming Integrated Circuitry | 2026-01-21 | 19454975 | Docketed New Case - Ready for Examination | parent 12557277 |
| METHODS AND APPARATUS FOR USING EPOXY-BASED OR INK-BASED SPACER TO SUPPORT LARGE DIE IN SEMICONDUCTOR DEVICES | 2026-01-21 | 19455491 | Docketed New Case - Ready for Examination | parent 12557679 |
| VOLATILE MEMORY DEVICES | 2026-01-20 | 19453920 | Docketed New Case - Ready for Examination | parent 12532461 |
| DEEP LEARNING ACCELERATION WITH MIXED PRECISION | 2026-01-20 | 19453136 | Docketed New Case - Ready for Examination | parent 12547882 |
| MANAGING WRITE DISTURB BASED ON IDENTIFICATION OF FREQUENTLY-WRITTEN MEMORY UNITS | 2026-01-20 | 19453511 | Docketed New Case - Ready for Examination | parent 12572311 |
| FAST MULTI-PAYLOAD-LENGTH ERROR-CORRECTING SYSTEM AND METHODS | 2026-01-20 | 19453469 | Docketed New Case - Ready for Examination | parent 12542567 |
| REDUNDANCY AND SWAPPING SCHEME FOR MEMORY REPAIR | 2026-01-20 | 19453544 | Docketed New Case - Ready for Examination | parent 12541440 |
| REDUCED POWER ADDRESSING | 2026-01-20 | 19453435 | Docketed New Case - Ready for Examination | parent 12625625 |
| POWER-OFF MONITOR FOR RELAXED BLOCK RETIREMENT IN A MEMORY SUB-SYSTEM | 2026-01-20 | 19454163 | Docketed New Case - Ready for Examination | parent 12554424 |
| STACKED CAPACITORS FOR SEMICONDUCTOR DEVICES AND ASSOCIATED SYSTEMS AND METHODS | 2026-01-16 | 19451452 | Docketed New Case - Ready for Examination | parent 12532781 |
| METHODS FOR FUSION BONDING SEMICONDUCTOR DEVICES TO TEMPORARY CARRIER WAFERS WITH HYDROPHOBIC REGIONS FOR REDUCED BOND STRENGTH, AND SEMICONDUCTOR DEVICE ASSEMBLIES FORMED BY THE SAME | 2026-01-16 | 19451346 | Docketed New Case - Ready for Examination | parent 12532708 |
| TIMING CIRCUIT HAVING TUNED TEMPERATURE DEPENDENCY | 2026-01-15 | 19450286 | Docketed New Case - Ready for Examination | parent 12531105 |
| METHODS OF FORMING MICROELECTRONIC DEVICES | 2026-01-15 | 19450646 | Docketed New Case - Ready for Examination | parent 12532778 |
| REUSE OF BAD BLOCKS FOR TASKS IN A MEMORY SUB-SYSTEM | 2026-01-15 | 19450414 | Docketed New Case - Ready for Examination | parent 12547332 |
| BLOCK CACHING WITH QUEUE IDENTIFIERS | 2026-01-15 | 19450458 | Docketed New Case - Ready for Examination | parent 12547346 |
| TOGGLING KNOWN PATTERNS FOR READING MEMORY CELLS IN A MEMORY DEVICE | 2026-01-14 | 19449262 | Docketed New Case - Ready for Examination | parent 12530146 |
| TEMPERATURE PROFILE TRACKING FOR ADAPTIVE DATA INTEGRITY SCAN RATE IN A MEMORY DEVICE | 2026-01-14 | 19449243 | Docketed New Case - Ready for Examination | parent 12530127 |
| MEMORY SYSTEM FOR BINDING DATA TO A MEMORY NAMESPACE | 2026-01-14 | 19448810 | Docketed New Case - Ready for Examination | parent 12566714 |
| SEMICONDUCTOR SYSTEMS WITH ANTI-WARPAGE MECHANISMS AND ASSOCIATED SYSTEMS, DEVICES, AND METHODS | 2026-01-14 | 19449206 | Docketed New Case - Ready for Examination | parent 12543572 |
| READ DISTURB TRACKING AMONG MULTIPLE ERASE BLOCKS COUPLED TO A SAME STRING | 2026-01-13 | 19447102 | Docketed New Case - Ready for Examination | parent 12530287 |
| MEMORY DEVICES INCLUDING CONDUCTIVE RAILS, AND RELATED METHODS AND ELECTRONIC SYSTEMS | 2026-01-12 | 19446434 | Docketed New Case - Ready for Examination | parent 12525534 |
| FAST MULTI-PAYLOAD-LENGTH ERROR-CORRECTING SYSTEM AND METHODS | 2026-01-12 | 19446261 | Docketed New Case - Ready for Examination | parent 12525993 |
| MEMORY BLOCK CHARACTERISTIC DETERMINATION | 2026-01-12 | 19446068 | Docketed New Case - Ready for Examination | parent 12525298 |
| CONDUCTIVE ORGANIC MODULE FOR SEMICONDUCTOR DEVICES AND ASSOCIATED SYSTEMS AND METHODS | 2026-01-12 | 19446774 | Docketed New Case - Ready for Examination | parent 12532774 |
| COMMANDS FOR TESTING ERROR CORRECTION IN A MEMORY DEVICE | 2026-01-09 | 19445199 | Docketed New Case - Ready for Examination | parent 12525990 |
| RELIABILITY BASED DATA VERIFICATION | 2026-01-09 | 19444480 | Docketed New Case - Ready for Examination | parent 12525304 |
| POWER MANAGEMENT FOR MEMORY DEVICES WITH PARTIALLY GOOD BLOCKS | 2026-01-08 | 19443934 | Docketed New Case - Ready for Examination | parent 12541311 |
| MEMORY WITH POST-PACKAGING MASTER DIE SELECTION | 2026-01-08 | 19443988 | Docketed New Case - Ready for Examination | parent 12524342 |
How to read this
Every row here is an application — a request the USPTO has not yet decided. In plain English: these filings show where Micron Technology, Inc.’s R&D effort is pointed right now, often 18–24 months before any product ships — but an application can be amended, abandoned, or rejected, and most confer no enforceable rights until granted. A “granted parent” tag means the filing continues a patent family that already has a grant — the new claims themselves are still pending. Filings are matched by applicant name, so work filed under subsidiary or research-entity names may not appear. Source: USPTO Open Data Portal (public).