Intel Corporation — Patent Applications
Published USPTO patent applications filed under applicant “Intel Corporation” — pending requests, not granted patents. Where a filing continues an already-granted parent, the parent’s number is shown.
Newest filing on this page: 2026-02-12. Last loaded from the USPTO Open Data Portal on 2026-06-11. This list is not refreshed on a schedule and was last loaded 135 days ago, so newer applications may be missing. USPTO publishes most applications about 18 months after they are filed.
Applications on file
Every row is a patent application — a pending request, not a granted patent. “Granted Parent” shows the parent patent number when a filing continues an already-granted family. Newest filing date first. Source: USPTO Open Data Portal (public).
| Title | Filed | Application # | Status | Granted Parent |
|---|---|---|---|---|
| IMAGE TOKEN PRUNING FOR MULTIMODAL FOUNDATION MODELS | 2026-02-12 | 19538554 | Docketed New Case - Ready for Examination | — |
| GATE-ALL-AROUND INTEGRATED CIRCUIT STRUCTURES HAVING DOPED SUBFIN | 2026-01-21 | 19454604 | Docketed New Case - Ready for Examination | parent 12575151 |
| BACKGROUND REPLACEMENT IN VIDEO CONFERENCE WITH OCCLUDED BACKGROUND PRIOR | 2026-01-16 | 19451750 | Docketed New Case - Ready for Examination | — |
| QUERY-AWARE MULTI-STAGE GRAPH CONTROL FOR RETRIEVAL-AUGMENTED GENERATION SYSTEMS | 2026-01-16 | 19451239 | Prosecution Suspended/Delayed | — |
| FIN TRIM PLUG STRUCTURES WITH METAL FOR IMPARTING CHANNEL STRESS | 2026-01-16 | 19451216 | Docketed New Case - Ready for Examination | parent 12588252 |
| EMBEDDED SEMICONDUCTIVE CHIPS IN RECONSTITUTED WAFERS, AND SYSTEMS CONTAINING SAME | 2026-01-15 | 19449820 | Docketed New Case - Ready for Examination | parent 12557665 |
| MICROELECTRONIC DEVICES DESIGNED WITH MOLD PATTERNING TO CREATE PACKAGE-LEVEL COMPONENTS FOR HIGH FREQUENCY COMMUNICATION SYSTEMS | 2026-01-14 | 19448590 | Docketed New Case - Ready for Examination | parent 12542358 |
| INTEGRATED CIRCUIT STRUCTURES WITH DEEP VIA STRUCTURE | 2026-01-13 | 19447479 | Docketed New Case - Ready for Examination | parent 12563774 |
| APPARATUS AND METHOD FOR UNCERTAINTY-AWARE CODE GENERATION USING LARGE LANGUAGE MODELS (LLMS) | 2026-01-13 | 19447995 | Prosecution Suspended/Delayed | — |
| CONTINUOUS GATE AND FIN SPACER FOR ADVANCED INTEGRATED CIRCUIT STRUCTURE FABRICATION | 2026-01-12 | 19446168 | Docketed New Case - Ready for Examination | parent 12557617 |
| DATA TRANSFERS AMONG PROCESSORS | 2026-01-12 | 19446460 | Prosecution Suspended/Delayed | — |
| FABRICATION OF GATE-ALL-AROUND INTEGRATED CIRCUIT STRUCTURES HAVING COMMON METAL GATES AND HAVING GATE DIELECTRICS WITH DIFFERENTIATED DIPOLE LAYERS | 2026-01-09 | 19444997 | Docketed New Case - Ready for Examination | parent 12563782 |
| SELECTIVE BACKSIDE RECESSING OF SOURCE AND DRAIN REGIONS | 2026-01-08 | 19443490 | Docketed New Case - Ready for Examination | parent 12563810 |
| ASSEMBLY OF 2XD MODULE USING HIGH DENSITY INTERCONNECT BRIDGES | 2026-01-08 | 19443417 | Docketed New Case - Ready for Examination | parent 12525562 |
| ELECTRICAL AND PHOTONIC INTEGRATED CIRCUITS ARCHITECTURE | 2026-01-08 | 19443757 | Docketed New Case - Ready for Examination | — |
| BUFFER COMMUNICATION FOR DATA BUFFERS SUPPORTING MULTIPLE PSEUDO CHANNELS | 2026-01-06 | 19441687 | Docketed New Case - Ready for Examination | parent 12524357 |
| INTEGRATED CIRCUIT STRUCTURES HAVING CONDUCTIVE STRUCTURES IN FIN ISOLATION REGIONS | 2026-01-06 | 19441378 | Docketed New Case - Ready for Examination | parent 12532538 |
| JUMPER GATE FOR ADVANCED INTEGRATED CIRCUIT STRUCTURES | 2026-01-05 | 19439982 | Docketed New Case - Ready for Examination | parent 12532726 |
| INTEGRATED CIRCUIT STRUCTURE HAVING ANTI-FUSE STRUCTURE | 2025-12-29 | 19435338 | Docketed New Case - Ready for Examination | parent 12519057 |
| PARALLEL PRUNING AND BATCH SORTING FOR SIMILARITY SEARCH ACCELERATORS | 2025-12-27 | 19433775 | Docketed New Case - Ready for Examination | — |
| LIQUID COOLING FOR INTEGRATED CIRCUIT PACKAGES | 2025-12-27 | 19433783 | Prosecution Suspended/Delayed | — |
| FRACTIONAL FILTERS FOR CONVOLUTIONAL NEURAL NETWORK PROCESSING | 2025-12-27 | 19433773 | Prosecution Suspended/Delayed | — |
| JOINT PERFORMANCE-POWER OPTIMIZATION FRAMEWORK FOR NEURAL PROCESSING UNIT BASED ARTIFICIAL INTELLIGENCE INFERENCE | 2025-12-26 | 19433546 | Prosecution Suspended/Delayed | — |
| TECHNIQUES TO ACCESS DEBUG AND/OR DIAGNOSTIC DATA FROM A PROCESSOR SYSTEM ON A CHIP | 2025-12-26 | 19433532 | Prosecution Suspended/Delayed | — |
| COMPUTE AND MEMORY BASED ARTIFICIAL INTELLIGENCE MODEL PARTITIONING USING INTERMEDIATE REPRESENTATION | 2025-12-26 | 19433399 | Docketed New Case - Ready for Examination | parent 12596583 |
| METHODS AND APPARATUS FOR TEMPERATURE BASED RE-TRAINING OF MEMORY ACCESS PARAMETERS | 2025-12-24 | 19432465 | Prosecution Suspended/Delayed | — |
| APPARATUS USED IN NON-AP STA | 2025-12-24 | 19432246 | Prosecution Suspended/Delayed | — |
| DYNAMIC FLASH REDUNDANCY FOR FIRMWARE LOADING | 2025-12-24 | 19432594 | Prosecution Suspended/Delayed | — |
| MEMORY DEVICES AND METHODS FOR MEMORY DEVICES | 2025-12-24 | 19432159 | Prosecution Suspended/Delayed | — |
| MEMORY-MAPPED I/O (MMIO) ADDRESS ALLOCATION | 2025-12-24 | 19432716 | Prosecution Suspended/Delayed | — |
| CAMM MODULE RETENTION FOR COMPRESSIVE MOUNT CONNECTOR AND HEATSINK | 2025-12-24 | 19432151 | Prosecution Suspended/Delayed | — |
| APPARATUSES USED IN AP MLD AND NON-AP MLD | 2025-12-24 | 19432241 | Prosecution Suspended/Delayed | — |
| RING MODULATOR BASELINE WANDER COMPENSATION | 2025-12-24 | 19432812 | Docketed New Case - Ready for Examination | parent 12556283 |
| SINGLE LAYER PLANAR MULTI-TURN SLICE COIL | 2025-12-24 | 19432221 | Prosecution Suspended/Delayed | — |
| QUICK USER DATAGRAM PROTOCOL (UDP) INTERNET CONNECTIONS (QUIC) PACKET OFFLOADING | 2025-12-24 | 19432820 | Docketed New Case - Ready for Examination | parent 12255974 |
| APPARATUS USED IN NON-AP STA | 2025-12-24 | 19432251 | Prosecution Suspended/Delayed | — |
| DYNAMIC MEMORY SHARING BETWEEN XPUS BASED ON SYSTEM HEURISTICS AND REAL TIME ADJUSTMENTS | 2025-12-24 | 19432194 | Prosecution Suspended/Delayed | — |
| APPARATUS, SYSTEM, AND METHOD OF BEACON TRANSMISSION TIME SHIFT | 2025-12-24 | 19432612 | Prosecution Suspended/Delayed | — |
| Caching Apparatus, Driver Apparatus, Transcoding Apparatus and Corresponding Devices, Methods and Computer Programs | 2025-12-23 | 19430354 | Docketed New Case - Ready for Examination | — |
| ROAMING ENHANCEMENTS | 2025-12-23 | 19432037 | Prosecution Suspended/Delayed | — |
| ULTRA SMALL MOLDED MODULE INTEGRATED WITH DIE BY MODULE-ON-WAFER ASSEMBLY | 2025-12-23 | 19431951 | Docketed New Case - Ready for Examination | parent 12525544 |
| ENHANCED IN-BAND ACTIVATION AND PROVISIONING OF DEVICES FOR OPENROAMING NETWORKS | 2025-12-23 | 19431595 | Docketed New Case - Ready for Examination | — |
| INTEGRATED CIRCUIT STRUCTURE WITH DIRECT BACKSIDE SOURCE OR DRAIN CONTACT | 2025-12-23 | 19431948 | Docketed New Case - Ready for Examination | — |
| CONFIGURABLE PROCESSOR ELEMENT ARRAYS FOR IMPLEMENTING CONVOLUTIONAL NEURAL NETWORKS | 2025-12-23 | 19430686 | Docketed New Case - Ready for Examination | parent 12554962 |
| METHODS AND APPARATUS FOR POWER CONTROL DURING MEDIA PLAYBACK | 2025-12-23 | 19431704 | Prosecution Suspended/Delayed | — |
| DISPLAY SYSTEM WITH PRIVACY BASED ON VIEWER POSITION | 2025-12-23 | 19431421 | Prosecution Suspended/Delayed | — |
| SCRAMBLING OF PIXEL DATA FOR VIDEO ENCRYPTION | 2025-12-23 | 19431638 | Prosecution Suspended/Delayed | — |
| INTEGRATED CIRCUIT ATTACHMENT MECHANISMS | 2025-12-23 | 19430372 | Prosecution Suspended/Delayed | — |
| ARCHITECTURE FOR COMBINING DUAL BIAS DIGITAL POWER AMPLIFIER (PA) CELLS | 2025-12-23 | 19430662 | Prosecution Suspended/Delayed | — |
| Semiconductor Apparatus, Semiconductor Device, Method for a Semiconductor Device, and Non-Transitory Computer-Readable Medium, Method, Apparatus and Device for a Computer System | 2025-12-22 | 19429691 | Prosecution Suspended/Delayed | — |
How to read this
Every row here is an application — a request the USPTO has not yet decided. In plain English: these filings show where Intel Corporation’s R&D effort is pointed right now, often 18–24 months before any product ships — but an application can be amended, abandoned, or rejected, and most confer no enforceable rights until granted. A “granted parent” tag means the filing continues a patent family that already has a grant — the new claims themselves are still pending. Filings are matched by applicant name, so work filed under subsidiary or research-entity names may not appear. Source: USPTO Open Data Portal (public).
How many Intel Corporation patent applications does this page show?
This page lists 50 U.S. patent applications Oxford Ledge has matched to Intel Corporation, of which 18 continue an already-granted patent family. It is not a count of everything the company has on file. Every row is an application (a pending request to the USPTO), not a granted patent.
What is the difference between a patent application and a granted patent?
A patent application is a pending request filed with the USPTO; a granted patent is one the USPTO has examined and issued. These pages track applications, which signal a company's R&D direction before any patent is granted.
Where does this patent data come from?
The USPTO Open Data Portal (public), matched to the company's applicant registrations.